Recent advances in the miniaturization of integrated circuits have led to smaller chip areas made available for devices. High density dynamic random access memory chips (DRAMs), for example, leave little room for the storage node of a memory cell. Yet, the storage node (capacitor) must be able to store a certain minimum charge, determined by design and operational parameters, to ensure reliable operation of the memory cell. It is thus increasingly important that capacitors achieve a high stored charge storage per unit area of the wafer. Accordingly, several techniques have been recently developed to increase the total charge capacity of the cell capacitor without significantly affecting the chip area occupied by the cell.
Traditionally, capacitors integrated into memory cells have been patterned after the parallel plate capacitor. An interelectrode dielectric material is deposited between two conductive layers, which form the capacitor plates or electrodes. The amount of charge stored on the capacitor is proportional to the capacitance, C=.epsilon..epsilon..sub.0 A/d, where .epsilon. is the dielectric constant of the capacitor dielectric, .epsilon..sub.0 is the vacuum permittivity, A is the electrode area, and d represents the spacing between electrodes. Some techniques for increasing capacitance therefore include the use of new materials characterized by high dielectric constants.
Other techniques concentrate on increasing the effective surface area of the electrodes by creating folding structures such as trench or stacked capacitors. Such structures better utilize the available chip area by creating three dimensional shapes to which the conductive plates and capacitor dielectric conform. For example, U.S. Pat. No. 5,340,765, issued to Dennison et al. and assigned to the assignee present invention, discloses a process for forming capacitor structures resembling cylindrical containers. A polycrystalline silicon (polysilicon) container is first formed, both the inside and outside surfaces of which are available for use as the bottom electrode. More complex structures, such as the container-within-container and multiple pin structures disclosed in U.S. Pat. No. 5,340,763, issued Aug. 23, 1994 to Dennison, may further increase electrode surface area and allow the extension of conventional fabrication materials to future generation memory devices. The capacitor dielectric and top electrode may then be successively deposited.
Electrode surface area may also be increased by providing a high surface area, rough texture to the electrode surface. One class of methods for providing rough electrode surfaces involves roughening polysilicon layers with preferential etch techniques. For example, U.S. Pat. No. 3,405,801, issued to Han et al., discloses a method of roughening a polysilicon layer by selectively etching at grain boundaries. Alternatively, U.S. Pat. No. 5,372,962, issued to Hirota et al., describes various selective etch processes for perforating a polysilicon layer.
Another class of electrode roughening techniques involves texturizing a conductive layer by formation of hemispherical grained (HSG) silicon. HSG silicon may be formed by a number of different methods, including gas phase nucleation and surface seeding. An extremely thin layer of oxide, for example, may serve as a seed layer for HSG growth to follow. Native oxide is allowed to grow over a previously deposited silicon layer. Polysilicon may then be deposited by low pressure chemical vapor deposition (LPCVD), and silicon grains grow preferentially about nucleation sites provided by the native oxide. Alternatively, nucleation sites may be provided by the deposition of dispersed particles as disclosed by U.S. Pat. No. 5,102,823, issued to Tuttle. In either case, during the initial stages of polysilicon deposition, the presence of these nucleation sites causes the formation of polysilicon nodules. During later stages of deposition, polysilicon will continue to coat the previously created nodules, resulting in stable, hemispherical polysilicon grains.
FIG. 1 is an exaggerated, close-up view of an HSG silicon layer 20 formed by an alternative, vacuum anneal process. A silicon layer is deposited and annealed at a critical temperature and pressure, inducing surface migration of silicon atoms. U.S. Pat. No. 5,407,534 issued to Thakur, for example, discloses one set of deposition and anneal parameters by which HSG silicon may be formed. Relatively large, hemispherical grains form by this redistribution, and the resultant HSG silicon layer 20 provides a much larger electrode surface area than planar polysilicon. As shown, the HSG silicon layer 20 is substantially contiguous, such than individual grains 22 tend to intersect one another. A capacitor dielectric may then be formed over the HSG silicon 20, and a conductive layer for the top electrode is deposited, in turn, over the capacitor dielectric.
While dielectric thickness ("d" of the capacitance formula set forth above) should be minimized in order to maximize capacitance, too thin a capacitor dielectric risks leakage current across the capacitor electrodes. Leakage current may result from pinholes in the dielectric and quantum tunneling effects, both of which phenomena are more likely to occur with thinner dielectrics. Thin capacitor dielectric layers are thus characterized by a low breakdown voltage, limiting the charge which may be stored on the bottom electrode before breakdown leakage occurs. Accordingly, capacitor dielectric layers may be characterized by a certain minimal thickness necessary to avoid breakdown, depending upon the selected dielectric material. Where the dielectric comprises silicon nitride (Si.sub.3 N.sub.4), for example, the layer should be at least about 50 .ANG..
FIG. 2 illustrates the HSG silicon 20 of FIG. 1 after a capacitor dielectric layer 23 has been deposited thereupon. The individual grains 22 of the HSG silicon 20 tend to intersect one another as illustrated, such that dielectric bridging occurs between grains, creating thicker dielectric between grains than over grain surfaces. The close-up view of FIG. 3 more clearly illustrates the discrepancy in dielectric 23 thickness in the boundary area 25 between individual hemispherical grains 22, and that over an upper surface area 26 of individual grains 22. The dielectric 23 of the boundary area 25 may reach twice as thick as the dielectric 23 in other areas, gradually reducing in thickness as the mouth of the boundary area widens.
If the dielectric 23 is deposited to the minimal thickness (e.g., 50-70 .ANG. of Si.sub.3 N.sub.4) in a boundary area 25, the dielectric 23 overlying the grains 22 will be too thin and lead to breakdown and operational data errors. Alternatively, when the dielectric 23 is deposited to the minimal thickness over HSG silicon grains, the dielectric of the boundary area 25 is too thick, leading to reduced capacitance and leaving too little room for conformal deposition (without voids or keyholes) of the top electrode material within the stacked capacitor. Too little capacitance for the memory cell may also lead to a high rate of soft data errors.
Accordingly, a need exists for a method of providing conformal dielectric layers for memory cell capacitors while maintaining high capacitance for the memory cell.